1. Field of the Invention
The present invention relates to memory devices, and particularly to a memory device that is capable of generating a ready signal that indicates a state in which specified data is ready for reading, or a state in which an operation of writing or erasing specified data has been finished.
2. Description of the Background Art
Because of the increasing memory capacities of memory devices (e.g., semiconductor memory devices), the time required from the input of a command about reading to the output (read) of the specified data (latency time) is becoming longer (in general, the time required for an operation of writing/erasing specified data is also becoming longer). In a conventional approach adopted for such memory devices, the host equipment sends a read command and then waits for a sufficient time before reading specified data from the memory (or, when an operation of writing or erasing specified data starts, the next processing is performed after waiting for a sufficient time).
However, in such a case, the specified data is read out while allowing for the longest latency time, and therefore the data transfer rate is considerably lowered.
To solve this problem, memory devices have been developed which output a ready signal to the host immediately after the data output has been readied. Such memory devices offer higher data transfer rates.
However, the memory devices that send ready signals involve considerable variations of latency time, depending upon the addresses specified in read operations. Because of the considerable variations of latency time, such memory devices are unsuitable for systems that are sensitive to timing.